Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement optimization for yield improvement of switched-capacitor analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Analog Integrated Circuits and Signal Processing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
The key performance of many analog circuits isdirectly related to accurate capacitor ratios. It is wellknown that capacitor ratio precision is greatly enhancedby paralleling identical size unit capacitors in a common-centroidgeometry. In this paper, a general algorithm forfitting arbitrary capacitor ratios in a common-centroidunit-capacitor array is presented. The algorithm givesspecial care to both non-integer and identical ratios inorder to minimize mismatch. A method for capacitancemismatch estimation based upon an oxide gradient modelis also introduced. It enables the comparison of differentunit-capacitor array assignments. Layout issues arediscussed with emphasis on a generic routing model.Both the algorithm and the mismatch estimation methodare implemented in an automatic capacitor arraygeneration tool.