A Low-Power Block-Matching Cell for VideoCompression

  • Authors:
  • M. Tartagni;A. Leone;R. Guerrieri

  • Affiliations:
  • DEIS, Università di Bologna, Viale Risorgimento, 2 I-40136—Bologna, Italy Tel: +39-051-209-3557 Fax: +39-051-209-3073;DEIS, Università di Bologna, Viale Risorgimento, 2 I-40136—Bologna, Italy Tel: +39-051-209-3557 Fax: +39-051-209-3073;DEIS, Università di Bologna, Viale Risorgimento, 2 I-40136—Bologna, Italy Tel: +39-051-209-3557 Fax: +39-051-209-3073

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2001

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Abstract

This paper describes theimplementation of a block-matching modulewith digital I/O. Algorithmic analysisdemonstrates that the precisionrequirements can be met by a compactcircuit that processes the signal in thecharge domain. The required conversionbetween voltages and charges is achieved byMOS capacitors. As a result, it can befabricated by any inexpensive digital CMOStechnology. A test chip has beenimplemented in a standard CMOS 1.6 μmtechnology and the measured energyconsumption is 1.2 nJ per block match usingan 8 \times 8 pixel matrix. Simulations ofthe same cell in 0.35 μm and 0.25 μmCMOS technology are presented, showing thescalability of the approach.