Introduction to algorithms
Analog VLSI signal processing: why, where, and how?
Journal of VLSI Signal Processing Systems - Joint special issue on Analog VLSI computation; also see Analog Integrated Circuits Signal Process., Vol. 6, No. 1
Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation
Analog Integrated Circuits and Signal Processing - Special issue on low voltage/low power design
Neural Networks: A Comprehensive Foundation
Neural Networks: A Comprehensive Foundation
Introduction to Reinforcement Learning
Introduction to Reinforcement Learning
Neuro-Dynamic Programming
Analog Integrated Circuits and Signal Processing
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Power management in energy harvesting sensor networks
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
A DP-network for optimal dynamic routing in network-on-chip
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Low power current-mode binary-tree asynchronous Min/Max circuit
Microelectronics Journal
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip
Proceedings of the Fifth International Workshop on Network on Chip Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Dynamic programming (DP) is a fundamental algorithm for complex optimization and decision-making in many engineering and biomedical systems. However, conventional DP computation based on digital implementation of the BeUman-Ford recursive algorithm suffers from the "curse of dimensionality" and substantial iteration delays which hinder utility in real-time applications. Previously, an ordinary differential equation system was proposed that transforms the sequential DP iteration into a continuous-time parallel computational network. Here, the network is realized using a CMOS current-mode analog circuit, which provides a powerful computational platform for power-efficient, compact, and high-speed solution of the Bellman formula. Test results for the fabricated DP optimization chip demonstrate a proof of concept for this solution approach. We also propose an error compensation scheme to minimize the errors attributed to nonideal current sources and device mismatch.