Winner-take-all networks of O(N) complexity
Advances in neural information processing systems 1
Scale-Space Properties of the Multiscale Morphological Dilation-Erosion
IEEE Transactions on Pattern Analysis and Machine Intelligence
Self-Organizing Maps
Robust Local Max-Min Filters by Normalized Power-Weighted Filtering
ICPR '04 Proceedings of the Pattern Recognition, 17th International Conference on (ICPR'04) Volume 1 - Volume 01
High-Precision Current-Based CMOS WTA/LTA Filters
CONIELECOMP '07 Proceedings of the 17th International Conference on Electronics, Communications and Computers
IEEE Transactions on Neural Networks
A CMOS current-mode dynamic programming circuit
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Ultra low power associative computing with spin neurons and resistive crossbar memory
Proceedings of the 50th Annual Design Automation Conference
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A novel, current-mode, binary-tree, asynchronous Min/Max circuit for application in nonlinear filters as well as in analog artificial neural networks is proposed. The relatively high precision above 99% can be achieved by eliminating the copying of the input signals from one layer to the other in the tree. In the proposed solution, the input signals are always directly copied to particular layers using separate signal paths. This makes the precision almost independent on the number of the layers i.e. the number of the inputs. The circuit is a flexible solution. The power dissipation, as well as data rate can be scaled up and down in a wide range. For an average value of the input currents of 20@mA and data rate of 11MHz the circuit dissipates 505@mW, while for the signals of 200nA and data rate of 500kHz the power dissipation is reduced to 1@mW. The prototype circuit with four inputs, realized in the CMOS 0.18@mm technology, occupies the area of 1800@mm^2.