Low power current-mode binary-tree asynchronous Min/Max circuit
Microelectronics Journal
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The design, simulation and implementation of highprecision current-based CMOS WTA/LTA filters are reported. The circuits are fast, compact and exhibit a high resolution and a low-power consumption. Therefore, they result attractive to be used in massive parallel processing structures, i.e. neural networks. HSPICE simulation results are presented in AMIS 0.5mm technology. In addition, experimental results are reported with monolithic NMOS and PMOS transistors.