Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Discrete Event Dynamic Systems
Checking Satisfiability of First-Order Formulas by Incremental Translation to SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Petri Net Analysis Using Boolean Manipulation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
SAT-Based Procedures for Temporal Reasoning
ECP '99 Proceedings of the 5th European Conference on Planning: Recent Advances in AI Planning
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Verifying analog oscillator circuits using forward/backward abstraction refinement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking of Analog/Mixed-Signal Circuits
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Verification of analog and mixed-signal circuits using symbolic methods
Verification of analog and mixed-signal circuits using symbolic methods
The Case for Analog Circuit Verification
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A SAT-based decision procedure for the boolean combination of difference constraints
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
An incremental and layered procedure for the satisfiability of linear arithmetic logic
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient satisfiability modulo theories via delayed theory combination
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Bounded model checking of software using SMT solvers instead of SAT solvers
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Instrumenting AMS assertion verification on commercial platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
First steps towards SAT-based formal analog verification
Proceedings of the 2009 International Conference on Computer-Aided Design
Analog/mixed-signal circuit verification using models generated from simulation traces
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
CalCS: SMT solving for non-linear convex constraints
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
| Hi-index | 0.00 |
This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The systems are modeled in VHDL-AMS, a hardware description language for AMS circuits. In this model, system safety properties are specified as assertion statements. The VHDL-AMS description is compiled into labeled hybrid Petri nets (LHPNs) in which analog values are modeled as continuous variables that can change at rates in a bounded range and digital values are modeled using Boolean signals. The verification method begins by transforming the LHPN model into an SMT formula composed of the initial state, the transition relation unrolled for a specified number of iterations, and the complement of the assertion in each set of state variables. When this formula evaluates to true, this indicates a violation of the assertion and an error trace is reported. This method has been implemented and preliminary results are promising.