The algorithmic analysis of hybrid systems
Theoretical Computer Science - Special issue on hybrid systems
A formal approach to nonlinear analog circuit verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The benefits of relaxing punctuality
Journal of the ACM (JACM)
Reasoning About Analog-Level Implementationsof Digital Systems
Formal Methods in System Design
A formal approach to verification of linear analog circuits wth parameter tolerances
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 7th International Workshop on Higher Order Logic Theorem Proving and Its Applications
Formal Verification of Synthesized Analog Designs
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Verification of transient response of linear analog circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Verification System for Transient Response of Analog Circuits Using Model Checking
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Verifying analog oscillator circuits using forward/backward abstraction refinement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A symbolic approach for mixed-signal model checking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Bounded model checking of analog and mixed-signal circuits using an SMT solver
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
AMT: a property-based monitoring tool for analog systems
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
PHAVer: algorithmic verification of hybrid systems past hytech
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
Towards assertion-based verification of heterogeneous system designs
Proceedings of the Conference on Design, Automation and Test in Europe
Realtime regular expressions for analog and mixed-signal assertions
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The industry trend appears to be moving towards designs that integrate large digital circuits with multiple analog/RF (radio frequency) interfaces. In the verification of these large integrated circuits, the number of nets that need to be monitored has been growing rapidly. Consequently, the mixed-signal design community has been feeling the need for AMS (Analog and Mixed Signal) assertions that can automatically monitor conformance with expected time-domain behavior and help in debugging deviations from the design intent. The main challenges in providing this support are (a) developing AMS assertion languages or AMS verification libraries, and (b) instrumenting existing commercial simulators to support assertion verification during simulation. In this article, we report two approaches: the first extends the Open Verification Library (OVL) to the AMS domain by integrating a new collection of AMS verification libraries; while the second extends SystemVerilog Assertions (SVA) by augmenting analog predicates into SVA. We demonstrate the use of AMS-OVL on the Cadence Virtuoso environment while emphasizing that our libraries can work in any environment that supports Verilog and Verilog-A. We also report the development of tool support for AMS-SVA using a combination of Cadence NCSIM and Synopsys VCS. We demonstrate the utility of both approaches on the verification of LP3918, an integrated power management unit (PMU) from National Semiconductors. We believe that in the absence of existing EDA (Electronic Design Automation) tools for AMS assertion verification, the proposed approaches of integrating our libraries and our tool sets with existing commercial simulators will be of considerable and immediate practical value.