Frequency Response Verification of Analog Circuits Using Global Optimization Techniques
Journal of Electronic Testing: Theory and Applications
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A verification system for transient response of analog circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Instrumenting AMS assertion verification on commercial platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A static verification approach for architectural integration of mixed-signal integrated circuits
Integration, the VLSI Journal
The Case for Analog Circuit Verification
Electronic Notes in Theoretical Computer Science (ENTCS)
ABCD-L: approximating continuous linear systems using boolean models
Proceedings of the 50th Annual Design Automation Conference
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We present an approach for formal verification of the DC and low frequency behavior of synthesized analog designs containing linear components and components whose behavior can be represented by piecewise linear models. A formal model of the structural description of a synthesized design is extracted from the sized component net-list produced by the synthesis tool, in terms of characteristic behavior of the components and various voltage and current laws. For the implementation to be correct, it must imply a formal model extracted from a user given behavior specification. Circuit implementation and expected behavior are both modeled in the PVS higher-order logic proof checker as linear functions and the PVS decision procedures are used to prove the implication.