Statecharts: A visual formalism for complex systems
Science of Computer Programming
The algorithmic analysis of hybrid systems
Theoretical Computer Science - Special issue on hybrid systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Reasoning About Analog-Level Implementationsof Digital Systems
Formal Methods in System Design
A formal approach to verification of linear analog circuits wth parameter tolerances
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering
Proceedings of the 7th International Workshop on Higher Order Logic Theorem Proving and Its Applications
Formal Verification of Synthesized Analog Designs
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Verification of transient response of linear analog circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Verification System for Transient Response of Analog Circuits Using Model Checking
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Methodology for the Digital Calibration of Analog Circuits and Systems: with Case Studies
Methodology for the Digital Calibration of Analog Circuits and Systems: with Case Studies
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In this paper we present a static method for verifying the proper integration of analog and mixed-signal macroblocks into an integrated circuit. We consider the problem in a setting where there is no golden reference for verifying the validity of the interconnections between the blocks. The proposed verification methodology relies on an abstract modeling of the functional behavior of the blocks and a set of consistency criteria defined over the composition of these abstract models. A new formalism called mode sequence chart (MSeqC) has been presented for capturing the behavior of the blocks at a level of abstraction that is suitable for interconnection verification. We present rules to compose the MSeqCs of each block in an integrated design and present three criteria that indicate possible interconnection faults. We present a tool called AMS-IV (AMS-interconnection verification) that takes the design netlist as input, the MSeqC model of each design block as reference, and tests the three criteria.