A verification system for transient response of analog circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model checking of analog systems using an analog specification language
Proceedings of the conference on Design, automation and test in Europe
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Instrumenting AMS assertion verification on commercial platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A static verification approach for architectural integration of mixed-signal integrated circuits
Integration, the VLSI Journal
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Analog/mixed-signal circuit verification using models generated from simulation traces
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Advanced methods for equivalence checking of analog circuits with strong nonlinearities
Formal Methods in System Design
Analog property checkers: a DDR2 case study
Formal Methods in System Design
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Conventional temporal logics like CTL, [1], used for specifying properties of digital systems are not well suited for property specification of analog systems. We present a new temporal logic for specifying properties of analog circuits. We call this logic Ana CTL (CTL for analog circuit verification). It is shown that Ana CTL is more suitable for specifying properties of analog systems than other temporal logics. The application of Ana CTL for verification of transient behavior of arbitrarily non-linear analog circuits has been presented. The transient response of a circuit under all possible input waveforms is represented as a finite state machine (FSM), by bounding and discretizing the continuous state space of an analog circuit. This FSM is created by means of repeated SPICE simulations. Algorithms have been developed to run Ana CTL queries on this discretized model. The structure of this FSM is well suited to represent the characteristics of analog circuits, and enables us to run complex queries including real-time constraints in polynomial time. The application of these methods on several real life analog circuits has been presented and we show that this system is a useful aid for detecting and debugging design errors.