Analog/mixed-signal circuit verification using models generated from simulation traces

  • Authors:
  • Scott Little;David Walter;Kevin Jones;Chris Myers

  • Affiliations:
  • University of Utah, Salt Lake City, UT;University of Utah, Salt Lake City, UT;University of Utah, Salt Lake City, UT;University of Utah, Salt Lake City, UT

  • Venue:
  • ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
  • Year:
  • 2007

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Abstract

Formal and semi-formal verification of analog/mixed-signal circuits is complicated by the difficulty of obtaining circuit models suitable for analysis. We propose a method to generate a formal model from simulation traces. The resulting model is conservative in that it includes all of the original simulation traces used to generate it plus additional behavior. Information obtained during the model generation process can also be used to refine the simulation and verification process.