Fundamentals of computer-aided circuit simulation
Fundamentals of computer-aided circuit simulation
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Analog Behavioral Modeling with the VERILOG-a Language
Analog Behavioral Modeling with the VERILOG-a Language
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
Three Decades of HDLs: Part I, CDL Through TI-HDL
IEEE Design & Test
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
The d/dt Tool for Verification of Hybrid Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Languages and tools for hybrid systems design
Foundations and Trends in Electronic Design Automation
Features of a tunnel diode oscillator at different temperatures
Microelectronics Journal
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Time Domain Verification of Oscillator Circuit Properties
Electronic Notes in Theoretical Computer Science (ENTCS)
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms
Electronic Notes in Theoretical Computer Science (ENTCS)
A tutorial on satisfiability modulo theories
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Analog/mixed-signal circuit verification using models generated from simulation traces
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Formal verification of tunnel diode oscillator with temperature variations
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SpaceEx: scalable verification of hybrid systems
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
PHAVer: algorithmic verification of hybrid systems past hytech
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
Analysis of digital circuits through symbolic reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques
Proceedings of the International Conference on Computer-Aided Design
The Designer's Guide to Verilog-AMS
The Designer's Guide to Verilog-AMS
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Analog and Mixed Signal (AMS) designs can be formally modeled as hybrid systems [45] and therefore formal verification techniques applicable to hybrid systems can be deployed to verify them. An extension to a formal verification approach applicable to hybrid systems is proposed to verify AMS designs [31]. In this approach formal verification (FV) is carried out on an AMS block using simulation traces from SPICE, a simulator widely used in the design and verification of analog and AMS blocks. A broader implication of this approach is the ability to carry out hierarchical verification using relevant simulation traces obtained at different abstraction levels of a design when modeled in appropriate platforms. This enables a seamless transition of design and verification artifacts from the highest level of abstraction to the lowest level of implementation at the transistor level of any AMS design and a resulting increase in confidence on the correctness of the final implementation. The proposed approach has been justified with its applications to different AMS design blocks. For each design, its formal model and the proposed computational techniques have been incorporated into CheckMate [11] - a FV tool for hybrid systems based on MATLAB and the Simulink/Stateflow framework from MathWorks. A further justification of the proposed approach is the resulting improvements observed in terms of reduced verification time for different specifications in each design.