Time Constrained Verification of Analog Circuits using Model-Checking Algorithms

Authors:
Darius Grabowski;Daniel Platte;Lars Hedrich;Erich Barke
Affiliations:
Institute of Microelectronic Systems, University of Hannover, Germany;Infineon Technologies AG, Munich, Germany;Institute for Computer Science, University of Frankfurt/Main, Germany;Institute of Microelectronic Systems, University of Hannover, Germany
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2006

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Abstract

In this contribution we present algorithms for model checking of analog circuits enabling the specification of time constraints. Furthermore, a methodology for defining time-based specifications is introduced. An already known method for model checking of integrated analog circuits has been extended to take into account time constraints. The method will be presented using three industrial circuits. The results of model checking will be compared to verification by simulation.