Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Verifying analog oscillator circuits using forward/backward abstraction refinement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A symbolic methodology for the verification of analog and mixed signal designs
Proceedings of the conference on Design, automation and test in Europe
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
PHAVer: algorithmic verification of hybrid systems past HyTech
International Journal on Software Tools for Technology Transfer (STTT)
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Verification of analog and mixed signal designs using online monitoring
IMS3TW '09 Proceedings of the 2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop
First steps towards SAT-based formal analog verification
Proceedings of the 2009 International Conference on Computer-Aided Design
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms
Electronic Notes in Theoretical Computer Science (ENTCS)
Advanced methods for equivalence checking of analog circuits with strong nonlinearities
Formal Methods in System Design
On simulation-based probabilistic model checking of mixed-analog circuits
Formal Methods in System Design
Analog property checkers: a DDR2 case study
Formal Methods in System Design
SpaceEx: scalable verification of hybrid systems
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
On behavioral model equivalence checking for large analog/mixed signal systems
Proceedings of the International Conference on Computer-Aided Design
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Heterogeneous verification of cyber-physical systems using behavior relations
Proceedings of the 15th ACM international conference on Hybrid Systems: Computation and Control
Proceedings of the International Conference on Computer-Aided Design
Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Compositional heterogeneous abstraction
Proceedings of the 16th international conference on Hybrid systems: computation and control
ABCD-L: approximating continuous linear systems using boolean models
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the 50th Annual Design Automation Conference
Formal verification of phase-locked loops using reachability analysis and continuization
Communications of the ACM
Proceedings of the International Conference on Computer-Aided Design
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We present an approach for verifying locking of charge-pump phase-locked loops by performing reachability analysis on a behavioral model of the circuit. Bounded uncertain parameters in the behavioral model make it possible to represent all possible behaviors of more detailed models. The dynamics of the behavioral model is hybrid (i.e., discrete and continuous) due to the switching of charge pumps that drive the analog control circuits. A unique feature of phase-locked loops compared to most other hybrid systems is that they require thousands of switchings in the continuous dynamics to converge sufficiently close to a limit cycle. This makes reachability analysis a challenging task since switches in the dynamics are expensive to compute and result in conservative overapproximations. We solve this problem by overapproximating the effects of the switching conditions with uncertain parameters in linear continuous models, a method we call continuization. Using efficient reachability algorithms for discrete-time linear systems, locking is verified over the complete range of possible initial states of a charge-pump PLL designed in 32nm CMOS SOI technology in comparable time required for Monte Carlo simulations of the same behavioral model.