A formal approach to nonlinear analog circuit verification
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CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
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Proceedings of the 7th International Conference on Computer Aided Verification
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VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the International Conference on Computer-Aided Design
Formal verification of phase-locked loops using reachability analysis and continuization
Communications of the ACM
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In this contribution two extensions for an analog equivalence checking method are proposed, enabling the checking of strongly nonlinear circuits with floating nodes such as digital library cells. Therefore, a structural recognition and mapping of eigenvalues, representing the dynamics, to circuit elements via circuit variables is presented. Additionally, the introduction of reachability analysis is significantly restricting the investigated state space to the relevant parts, avoiding false negatives. The newly introduced methods are compared to existing ones by application to industrial examples.