HYTECH: A Model Checker for Hybrid Systems
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Verifying analog oscillator circuits using forward/backward abstraction refinement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Bounded model checking of analog and mixed-signal circuits using an SMT solver
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
PHAVer: algorithmic verification of hybrid systems past hytech
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
Formal verification of phase-locked loops using reachability analysis and continuization
Proceedings of the International Conference on Computer-Aided Design
On behavioral model equivalence checking for large analog/mixed signal systems
Proceedings of the International Conference on Computer-Aided Design
Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques
Proceedings of the International Conference on Computer-Aided Design
Formal verification of analog circuit parameters across variation utilizing SAT
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a SPICE-type circuit simulation problem as a satisfiability problem. We start with a circuit level netlist, capture the non-linear behavior of the circuits at the transistor level via conservative approximations and transform the simulation problem into a search problem that can be exhaustively explored via a SAT solver. Thus, for DC as well as fixed time-step based transient and periodic steady state (PSS) simulation formulations, the solutions produced by the solver are formal in nature. We also present algorithms for abstraction refinement and smart interval generation to improve the computational efficiency of our proposed solution scheme. We have implemented our ideas into a tool called fSpice which is the first attempt at building a formal SPICE engine. We demonstrate the applicability of our ideas by showing experimental results using pruned versions of real designs that faced challenges during chip tape-out.