Computer Vision and Image Understanding
Ridge Regression Learning Algorithm in Dual Variables
ICML '98 Proceedings of the Fifteenth International Conference on Machine Learning
Support vector machines for analog circuit performance representation
Proceedings of the 40th annual Design Automation Conference
All-Digital Frequency Synthesizer in Deep-Submicron CMOS
All-Digital Frequency Synthesizer in Deep-Submicron CMOS
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Dlib-ml: A Machine Learning Toolkit
The Journal of Machine Learning Research
Formal verification of phase-locked loops using reachability analysis and continuization
Proceedings of the International Conference on Computer-Aided Design
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Approximate Confidence and Prediction Intervals for Least Squares Support Vector Regression
IEEE Transactions on Neural Networks
Classifying circuit performance using active-learning guided support vector machines
Proceedings of the International Conference on Computer-Aided Design
Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques
Proceedings of the International Conference on Computer-Aided Design
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The emergence of digitally-intensive analog circuits introduces new challenges to formal verification due to increased digital design content, and non-ideal digital effects such as finite resolution, round-off error and overflow. We propose a machine learning approach to convert digital blocks to conservative analog approximations via the use of kernel ridge regression. These learned models are then adopted in a hybrid formal reachability analysis framework where the support function based manipulations are developed to efficiently handle the large linear portion of the design and the more general satisfiability modulo theories technique is applied to the remaining nonlinear portion. The efficiency of the proposed method is demonstrated for the locked time verification of a digitally intensive phase locked loop.