All-Digital Frequency Synthesizer in Deep-Submicron CMOS

A phase-domain all-digital phase-locked loop architecture without reference clock retiming

IEEE Transactions on Circuits and Systems II: Express Briefs

All digital-quadrature-modulator based wideband wireless transmitters

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs

Proceedings of the 47th Design Automation Conference

Theory of flying-adder frequency synthesizers-part I: modeling, signals' periods and output average frequency

IEEE Transactions on Circuits and Systems Part I: Regular Papers

A technique to reduce phase/frequency modulation bandwidth in a polar RF transmitter

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Observer-controller digital PLL

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Effect of reference clock jitter and demonstration of near image-free operation for the ADPLL

IEEE Transactions on Circuits and Systems II: Express Briefs

Controlled-precision pure-digital square-wave frequency synthesizer

PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation

A 5 GHz 90-nm CMOS all digital phase-locked loop

Analog Integrated Circuits and Signal Processing

Spatially oversampled TDC with digital resolution enhancement

Analog Integrated Circuits and Signal Processing

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis

Proceedings of the 50th Annual Design Automation Conference

Glitch-free NAND-based digitally controlled delay-lines

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology

Analog Integrated Circuits and Signal Processing