A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Digital Signal Processing
All-Digital Frequency Synthesizer in Deep-Submicron CMOS
All-Digital Frequency Synthesizer in Deep-Submicron CMOS
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A digital resolution enhancement technique for time-to-digital converters (TDC) is proposed. This involves a simultaneous multi-channel measurement of a time interval with low complexity TDC of varying low resolutions. The coarse outputs of each converter are digitally post-processed to obtain an output whose precision is much better than that of the individual converters. Three post-processing algorithms are proposed and their limitations in presence of converter non-idealities are analyzed. A prototype system with 8 channels is implemented in 90 nm CMOS. 40MS/s output of each channel is algorithmically combined to obtain over 2.2---3X measured improvement in the resolution in 4/6/8 channel modes, validating the system principle. The chip occupies 0.3 mm2 and draws up to a maximum of 4 mA from a 1.2 V supply.