Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods

Authors:
D. Walter;S. Little;C. Myers;N. Seegmiller;T. Yoneda
Affiliations:
Univ. of Northern Philippines, Vigan;-;-;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2008

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Abstract

This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising.