K-d trees for semidynamic point sets
SCG '90 Proceedings of the sixth annual symposium on Computational geometry
Model checking
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
The Spice Book
A verification system for transient response of analog circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model checking of analog systems using an analog specification language
Proceedings of the conference on Design, automation and test in Europe
FSM model abstraction for analog/mixed-signal circuits by learning from I/O trajectories
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Formal verification of phase-locked loops using reachability analysis and continuization
Proceedings of the International Conference on Computer-Aided Design
Analysis of digital circuits through symbolic reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the International Conference on Computer-Aided Design
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In this paper a novel approach to discrete state space modeling of nonlinear analog circuits is presented, based on the introduction of an underlying discrete analog transition structure (DATS) and the related optimization problem of accurately representing a nonlinear analog circuit with a DATS. Starting from a circuit netlist, a partitioning of the state space to the discrete model is generated parallel and orthogonal to the trajectories of the state space dynamics. Therefore, compared to previous approaches, a significantly higher accuracy of the model is achieved with a lower number of states. The mapping of the partitioning to a DATS enables the application of formal verification algorithms. Experimental validations show the soundness of the approach with an increase in accuracy between a factor of 4 to 10 compared to the state of the art. A model checking case study illustrates the application of the new discretization algorithm to identify a hidden circuit design error.