Fundamentals of computer-aided circuit simulation
Fundamentals of computer-aided circuit simulation
Introduction to algorithms
Theoretical Computer Science
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
On Discrete Modeling and Model Checking for Nonlinear Analog Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Open Computation Tree Logic for Formal Verification of Modules
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Formal Verification of Synthesized Analog Designs
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Heuristic Search + Local Model Checking in Selective mu-Calculus
IEEE Transactions on Software Engineering
Verification of transient response of linear analog circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Verification System for Transient Response of Analog Circuits Using Model Checking
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
The open family of temporal logics: Annotating temporal operators with input constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Verifying analog oscillator circuits using forward/backward abstraction refinement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
On behavioral model equivalence checking for large analog/mixed signal systems
Proceedings of the International Conference on Computer-Aided Design
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the International Conference on Computer-Aided Design
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a method for application of formal techniques like model checking and equivalence checking for validation of the transient response of nonlinear analog circuits. We propose a temporal logic called Ana CTL (computational tree logic for analog circuit verification) which is suitable for specifying properties specific to analog circuits. The application of Ana CTL for validation of transient behavior of arbitrarily nonlinear analog circuits is presented. The transient response of a circuit under all possible input waveforms is represented as a finite state machine (FSM), by bounding and discretizing the continuous state space of an analog circuit. We have developed algorithms to run Ana CTL queries on this discretized model using search-based methods which reduce the runtime considerably by avoiding creation of the whole FSM. The application of these methods on several real-life analog circuits is presented and we show that this system is a useful aid for detecting and debugging early design errors. We also present methods for checking the equivalence of transient response of two analog circuits. The behavior of two different analog circuits can rarely be exactly similar. Hence, we introduce a notion of approximate equivalence. A query language for checking different notions of user-definable approximate equivalence is presented which extends the syntax of the Ana CTL model checking language. In its extended form, Ana CTL can be used combining model checking with equivalence checking.