Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A practical approach for monitoring analog circuits
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Planning Algorithms
A verification system for transient response of analog circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Coverage-guided test generation for continuous and hybrid systems
Formal Methods in System Design
Verification of analog and mixed signal designs using online monitoring
IMS3TW '09 Proceedings of the 2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop
Time Domain Verification of Oscillator Circuit Properties
Electronic Notes in Theoretical Computer Science (ENTCS)
AMT: a property-based monitoring tool for analog systems
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
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Because of complexity of analog circuits, their verification presents many challenges. We propose a runtime verification algorithm to verify design properties of nonlinear analog circuits. Our algorithm is based on performing exploratory simulations in the state-time space using the Time-augmented Rapidly Exploring Random Tree (TRRT) algorithm. The proposed runtime verification methodology consists of i) incremental construction of the TRRT to explore the state-time space and ii) use of an incremental online monitoring algorithm to check whether or not the incremented TRRT satisfies or violates specification properties at each iteration. In comparison to the Monte Carlo simulations, for providing the same state-space coverage, we utilize a logarithmic order of memory and time.