Model-checking in dense real-time
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
A formal approach to verification of linear analog circuits wth parameter tolerances
Proceedings of the conference on Design, automation and test in Europe
Analog circuit sizing based on formal methods using affine arithmetic
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
The common fragment of CTL and LTL
FOCS '00 Proceedings of the 41st Annual Symposium on Foundations of Computer Science
Methods and Applications of Interval Analysis (SIAM Studies in Applied and Numerical Mathematics) (Siam Studies in Applied Mathematics, 2.)
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Real time temporal logic: past, present, future
FORMATS'05 Proceedings of the Third international conference on Formal Modeling and Analysis of Timed Systems
Verifying start-up conditions for a ring oscillator
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm
Proceedings of the Conference on Design, Automation and Test in Europe
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Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog and mixed signal systems is a challenging task that requires lots of expertise and deep understanding of their behavior. In this paper, we present a run-time verification methodology based on monitoring the behavior (solution flow) of analog circuits. Monitors are deterministic timed automata that can be synthesized from temporal properties. For illustration purposes, we applied our methodology on the verification of the oscillation property of a tunnel diode oscillator.