Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A practical approach for monitoring analog circuits
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Verifying analog oscillator circuits using forward/backward abstraction refinement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
PHAVer: algorithmic verification of hybrid systems past hytech
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Global convergence analysis of mixed-signal systems
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
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Recently, researchers at Rambus proposed a ring-oscillator example as a challenge problem for analog verification: they asked researchers to identify conditions that will ensure that the oscillator is free from lock-up. We present a solution to this challenge problem. Our approach is primarily pencil-and-paper analysis. We prove properties of the oscillator circuit, and then use numerical computation to determine parameter values for which correct operation is guaranteed. In addition to answering the challenge question, our approach uncovered anomalous behaviors that could cause the circuit to fail to oscillate but that would be hard to detect by standard, simulation-based, design practices.