Analog circuit sizing based on formal methods using affine arithmetic

Authors:
Andreas Lemke;Lars Hedrich;Erich Barke
Affiliations:
University of Hanover, Hannover, Germany;University of Hanover, Hannover, Germany;University of Hanover, Hannover, Germany
Venue:
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Year:
2002

Citing 2
Cited 8

Practical synthesis of high-performance analog circuits

Practical synthesis of high-performance analog circuits
A formal approach to verification of linear analog circuits wth parameter tolerances

Proceedings of the conference on Design, automation and test in Europe

Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling

Proceedings of the 40th annual Design Automation Conference
Refinement of Mixed-Signal Systems with Affine Arithmetic

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Towards formal verification of analog designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A practical approach for monitoring analog circuits

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty

Proceedings of the 43rd annual Design Automation Conference
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools

Proceedings of the 43rd annual Design Automation Conference
Verification of mixed-signal systems with affine arithmetic assertions

VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a novel approach to optimization-based variation-tolerant analog circuit sizing. Using formal methods based on affine arithmetic, we calculate guaranteed bounds on the worst-case behavior and deterministically find the global optimum of the sizing problem by means of branch-and-bound optimization. To solve the nonlinear circuit equations with parameter variations, we define a novel affine-arithmetic Newton operator that gives a significant improvement in computational efficiency over an implementation using interval arithmetic. The calculation of guaranteed worst-case bounds and the global optimization are demonstrated by a prototype implementation.