Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
PCI System Architecture
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Formal verification of module interfaces against real time specifications
Proceedings of the 39th annual Design Automation Conference
Model checking on state transition diagram
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
The open family of temporal logics: Annotating temporal operators with input constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language-Based High Level Transaction Extraction on On-chip Buses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A verification system for transient response of analog circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Modules of large VlSI circuits are often designed by different designers spread across the globe. One of the main challenges of the designer is to guarantee that the module he/she designs will work correctly in the global design, the details of which, is often unknown to him/her. Modules are open systems whose behavior is subject to the inputs it receives from its environment. It has been shown that verification of open systems (modules) is computationally very hard (EXPTIME complete [7]) when we consider all possible environments. On the other hand we show that integrating the specification of the properties to be verified with the specification of only the valid input patterns (under which the module is expected to function correctly) gives us a powerful syntax which can be verified in polynomial time. We call the proposed logic Open-CT (CT for open systems). The convenience of being able to specify the property and the environment in a unified way in Open-CT is demonstrated through a study of the PCI Bus properties. We present a symbolic BDD-based verification scheme for checking Open-CT formulas, and present experimental results on modules from the Texas-97 Verification Benchmark circuits [12].