Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Symbolic Model Checking
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
On the complexity of modular model checking
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
Open Computation Tree Logic for Formal Verification of Modules
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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Computation Tree Logic (CTL) model checking is sensitive to state explosion. Conventionally, CTL semantics is defined over Kripke structure where each state is labelled with all the atomic propositions. For open systems, this necessitates input labeling of the states. In contrast, the common model, which is used for sequential circuit design, is the finite state machine (FSM) model, or equivalently, the state transition diagram (STD), where the inputs are associated not with the states but with the transitions. Thus, to use a conventional CTL model checker, the STD has to be converted first to the Kripke structure and then applying the model checking algorithm on the Kripke structure. The need for associating input labels to the states results in state explosion which finally tells upon the model checking efficiency. The paper presents the CTL semantics over STD structures and develops a model checking algorithm which works directly over the STD. A performance gain over conventional model checking by an exponential factor results in the process, especially for open systems.