Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
In transition from global to modular temporal reasoning about programs
Logics and models of concurrent systems
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modalities for model checking (extended abstract): branching time strikes back
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Formal verification of module interfaces against real time specifications
Proceedings of the 39th annual Design Automation Conference
Decomposing refinement proofs using assume-guarantee reasoning
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Visual Specifications for Modular Reasoning about Asynchronous Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Characterizing Correctness Properties of Parallel Programs Using Fixpoints
Proceedings of the 7th Colloquium on Automata, Languages and Programming
Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Generalized Quantitative Temporal Reasoning: An Automata Theoretic Approach
TAPSOFT '97 Proceedings of the 7th International Joint Conference CAAP/FASE on Theory and Practice of Software Development
A Proof Technique for Rely/Guarantee Properties
Proceedings of the Fifth Conference on Foundations of Software Technology and Theoretical Computer Science
MCTL - An Extension of CTL for Modular Verification of Concurrent Systems
Temporal Logic in Specification
On the Competeness of Compositional Reasoning
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Quantitative Temporal Reasoning
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Verifying the Correctness of AADL Modules Using Model Checking
Stepwise Refinement of Distributed Systems, Models, Formalisms, Correctness, REX Workshop
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
Parametric Quantitative Temporal Reasoning
LICS '99 Proceedings of the 14th Annual IEEE Symposium on Logic in Computer Science
Open Computation Tree Logic for Formal Verification of Modules
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Formal Verification of Modules under Real Time Environment Constraints
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
P-A logic: a compositional proof system for distributed programs
Distributed Computing
A verification system for transient response of analog circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Assume-guarantee style verification of modules relies on the appropriate modeling of the interaction of the module with its environment. Popular temporal logics such as Computation Tree Logic (CTL) and Linear Temporal Logic (LTL) that were originally defined for closed systems (Kripke structures) do not make any syntactic discrimination between input and output variables. As a result, these logics and their recent derivatives (such as System Verilog, Sugar, Forspec, etc) permit the specification of properties that have some semantic problems when interpreted over open systems or modules. These semantic problems are quite common in practice, but are computationally hard to detect within a given specification. In this article, we propose a new style for writing temporal specifications of open systems that helps the designer to avoid most of these problems. In the proposed style, the basic temporal operators (such as next and until) are annotated with assume constraints over the input variables. We formalize this style through an extension of LTL, namely Open-LTL and an extension of CTL with fairness, called Open-CTL. We show that this simple syntactic separation between the assume and the guarantee achieves the desired results. We show that the proposed style can be integrated with traditional symbolic model-checking techniques and present a complete tool for the verification of Verilog RTL modules in isolation.