Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Real-time logics: complexity and expressiveness
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Model checking
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Quantitative Temporal Reasoning
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Open Computation Tree Logic for Formal Verification of Modules
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
The open family of temporal logics: Annotating temporal operators with input constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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One of the main concerns of the designer of a circuit module is to guarantee that the interface of the module conforms to specific protocols (such as PCI Bus, AMBA bus or Ethernet) by which it interacts with its environment. The computational complexity of verifying such open systems under all possible environments has been shown to be very hard (EXPTIME complete [10]). On the other hand, designers are typically required to guarantee correct behavior only for specific valid behaviors of the environment (such as a valid PCI Bus environment). Designers attempt to model these behaviors through an appropriate test bench for the module. In this paper we present a module verifier tool based on a proposed real time temporal logic called Open-RTCTL, which allows combined specification of the correctness properties and the input environments. The tool accepts the design in a subset of Verilog. By making the designer specify the environment constraints, we are able to verify a module in isolation, and thereby avoid the state explosion problem due to composition of modules. We present experimental results on modules from the Texas-97 Benchmark circuits [14] to demonstrate the space/time efficiency of the tool.