Model checking of CTL formulae under liveness assumptions
14th International Colloquium on Automata, languages and programming
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In transition from global to modular temporal reasoning about programs
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EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Circular Compositional Reasoning about Liveness
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
On the Competeness of Compositional Reasoning
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Concurrency Verification: Introduction to Compositional and Non-compositional Methods
Concurrency Verification: Introduction to Compositional and Non-compositional Methods
The Influence of Software Module Systems on Modular Verification
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Visual Specifications for Modular Reasoning about Asynchronous Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Verified systems by composition from verified components
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The open family of temporal logics: Annotating temporal operators with input constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Component-based hardware/software co-verification for building trustworthy embedded systems
Journal of Systems and Software
The Beginning of Model Checking: A Personal Perspective
25 Years of Model Checking
Component-Based Abstraction and Refinement
ICSR '08 Proceedings of the 10th international conference on Software Reuse: High Confidence Software Reuse in Large Systems
Machine-Verifiable Responsiveness
Electronic Notes in Theoretical Computer Science (ENTCS)
On the completeness of compositional reasoning methods
ACM Transactions on Computational Logic (TOCL)
Compositional reasoning for hardware/software co-verification
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Concurrency, Compositionality, and Correctness
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The explosion in the number of states due to several interacting components limits the application of model checking in practice. Compositional reasoning ameliorates this problem by reducing reasoning about the entire system to reasoning about individual components. Such reasoning is often carried out in the assume-guarantee paradigm: each component guarantees certain properties based on assumptions about the other components. Na茂ve applications of this reasoning can be circular and, therefore, unsound. We present a new rule for assume-guarantee reasoning, which is sound and complete. We show how to apply it, in a fully automated manner, to properties specified as synchronous timing diagrams. We show that timing diagram properties have a natural decomposition into assume-guarantee pairs, and liveness restrictions that result in simple subgoals which can be checked efficiently. We have implemented our method in a timing diagram analysis tool, which carries out the compositional proof in a fully automated manner. Initial applications of this method have yielded promising results, showing substantial reductions in the space requirements for model checking.