Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams

VHDL/S—integrating statecharts, timing diagrams, and VHDL

EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications

Specification and verification of VHDL-based system-level hardware designs

Specification and validation methods

Symbolic timing verification of timing diagrams using Presburger formulas

DAC '97 Proceedings of the 34th annual Design Automation Conference

Tamagotchis Need Not Die - Verification of STATEMENT Design

TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems

Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams

TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems

Specification and verification of concurrent systems in CESAR

Proceedings of the 5th Colloquium on International Symposium on Programming

Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable

CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification

Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic

Logic of Programs, Workshop

Model Checking Synchronous Timing Diagrams

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design