Modalities for model checking: branching time logic strikes back
Science of Computer Programming
Specification and verification of concurrent programs by A∀automata
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
ACM Transactions on Programming Languages and Systems (TOPLAS)
Specification and verification of VHDL-based system-level hardware designs
Specification and validation methods
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Concurrency verification: introduction to compositional and noncompositional methods
Concurrency verification: introduction to compositional and noncompositional methods
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Feature integration using a feature construct
Science of Computer Programming
Revised Lectures from the International Symposium on Compositionality: The Significant Difference
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
What Do Message Sequence Charts Mean?
FORTE '93 Proceedings of the IFIP TC6/WG6.1 Sixth International Conference on Formal Description Techniques, VI
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
An Automata Based Interpretation of Live Sequence Charts
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Model Checking of Message Sequence Charts
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Efficient Decompositional Model Checking for Regular Timing Diagrams
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Deciding Properties for Message Sequence Charts
FoSSaCS '98 Proceedings of the First International Conference on Foundations of Software Science and Computation Structure
On the Competeness of Compositional Reasoning
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Shared Variables Interaction Diagrams
Proceedings of the 16th IEEE international conference on Automated software engineering
Events and Constraints: A Graphical Editor for Capturing Logic Requirements of Programs
RE '01 Proceedings of the Fifth IEEE International Symposium on Requirements Engineering
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A unified approach to hardware verification through a heterogeneous logic of design diagrams
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The open family of temporal logics: Annotating temporal operators with input constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the completeness of compositional reasoning methods
ACM Transactions on Computational Logic (TOCL)
Temporal modalities for concisely capturing timing diagrams
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Local symmetry and compositional verification
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
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We propose a framework that closely ties together visual specification and modular reasoning of asynchronous systems. The basis of the framework is a new notation, called Modular Timing Diagrams (MTD's), for specifying the universal properties about causality and timing of events in an asynchronous system. MTD's are complementary in nature to Message Sequence Charts, that are typically used to specify existential properties. Our framework includes two algorithms for formal reasoning with MTD's. The first is an efficient polynomial-time model checking algorithm. The second is an algorithm for automatically generating an assume-guarantee partitioning of an MTD, that exploits its inherent decompositional structure. We show how to use this decomposition for modular reasoning withMTD properties in conjunction with an asynchronous compositional reasoning rule. To illustrate the notation and our method, we describe a case study where we specified telephony features, suchas call forwarding with MTD's, and verified these properties on an asynchronous telephony model. The compositional reasoning methods led to savings of 15%-80% in verification times, and comparable savings in space.