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Visual Specifications for Modular Reasoning about Asynchronous Systems
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A scenario based notation for specifying temporal properties
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User guidance for creating precise and accessible property specifications
Proceedings of the 14th ACM SIGSOFT international symposium on Foundations of software engineering
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Graphical scenarios for specifying temporal properties: an automated approach
Automated Software Engineering
Runtime monitoring of web service conversations
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Failure-free coordinators synthesis for component-based architectures
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TEPE: a SysML language for time-constrained property modeling and formal verification
ACM SIGSOFT Software Engineering Notes
Requirements Traceability within Model-Based Testing: Applying Path Fragments and Temporal Logic
International Journal of Embedded and Real-Time Communication Systems
A formal approach for run-time verification of web applications using scope-extended LTL
Information and Software Technology
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Abstract: A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement of the correctness requirements to be checked in temporal logic. Expressing non-trivial requirements in logic, however, can be challenging. To address this problem, we developed a graphical tool, the TimeLine Editor, that simplifies the formalization of certain kinds of requirements. A series of events and required system responses are placed on a timeline. The user converts the timeline specification automatically into a test automaton, that can be used directly by a logic model checker, or for traditional test-sequence generation. We have used the TimeLine Editor to verify the call processing code for Lucent's PathStar Access Server against the TelCordia LSSGR standards. The TimeLine editor simplified the task of converting a large body of English prose requirements into formal, yet readable, logic requirements.