Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal verification of embedded systems based on CFSM networks
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal Methods in System Design - Special issue on The First Federated Logic Conference (FLOC'96), part II
System architecture directions for networked sensors
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Component-based software engineering: putting the pieces together
Component-based software engineering: putting the pieces together
Component Software: Beyond Object-Oriented Programming
Component Software: Beyond Object-Oriented Programming
Executable UML: A Foundation for Model-Driven Architectures
Executable UML: A Foundation for Model-Driven Architectures
Formal Description Technique Lotos: Results of the Esprit Sedos Project
Formal Description Technique Lotos: Results of the Esprit Sedos Project
A Survey of Digital Design Reuse
IEEE Design & Test
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
ObjectCheck: A Model Checking Tool for Executable Object-Oriented Software System Designs
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Modular verification of software components in C
Proceedings of the 25th International Conference on Software Engineering
Verified systems by composition from verified components
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
A Formal Verification Methodology for IP-based Designs
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Component-based software engineering for embedded systems
Proceedings of the 27th international conference on Software engineering
Translation-based co-verification
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Embedded architecture description language
Journal of Systems and Software
Componentizing hardware/software interface design
Proceedings of the Conference on Design, Automation and Test in Europe
An automata-theoretic approach to hardware/software co-verification
FASE'10 Proceedings of the 13th international conference on Fundamental Approaches to Software Engineering
Efficient reachability analysis of büchi pushdown systems for hardware/software co-verification
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Hi-index | 0.00 |
We present a novel component-based approach to hardware/software co-verification of embedded systems using model checking. Embedded systems are pervasive and often mission-critical, therefore, they must be highly trustworthy. Trustworthy embedded systems require extensive verification. The close interactions between hardware and software of embedded systems demand co-verification. Due to their diverse applications and often strict physical constraints, embedded systems are increasingly component-based and include only the necessary components for their missions. In our approach, a component model for embedded systems which unifies the concepts of hardware IPs (i.e., hardware components) and software components is defined. Hardware and software components are verified as they are developed bottom-up. Whole systems are co-verified as they are developed top-down. Interactions of bottom-up and top-down verification are exploited to reduce verification complexity by facilitating compositional reasoning and verification reuse. Case studies on a suite of networked sensors have shown that our approach facilitates major verification reuse and leads to order-of-magnitude reduction on verification complexity.