High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
Open Computation Tree Logic for Formal Verification of Modules
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Proposal for Transaction-Level Verification with Component Wrapper Language
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
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With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of the main problems in SoC verification is to verify whether the interface of a block works properly in its intended system. Transaction-based verification methodologies have been proposed to deal with this problem, and they allow users creating tests and writing test benches more easily. Furthermore, verifying interface designs in transaction level is very efficient. Previous work creates extractor manually for one on-chip bus (OCB), and the extra efforts are needed for another OCBs. In this paper, we present a languagebased methodology to specify the bus behaviors in transaction level. Then the actual signals on the buses can be extracted to a higher level of abstraction. The bus behaviors displayed in transaction level significantly reduce the verification efforts for verification engineers. Furthermore, the corresponding transaction extractors are automatically generated. We demonstrate the success of our approach on AMBA AHB and Sonics' OCP buses.