Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice

  • Authors:

  • Subhankar Mukherjee;Pallab Dasgupta;Siddhartha Mukhopadhyay;Scott Little;John Havlicek;Srikanth Chandrasekaran

  • Affiliations:

  • Indian Institute of Technology Kharagpur;Indian Institute of Technology Kharagpur;Indian Institute of Technology Kharagpur;Freescale Semiconductor;Freescale Semiconductor;Freescale Semiconductor

  • Venue:
  • ACM Transactions on Design Automation of Electronic Systems (TODAES)
  • Year:
  • 2012

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Abstract

The verification community anticipates the adoption of assertions in the Analog and Mixed-Signal (AMS) domain in the near future. Several questions need to be answered before AMS assertions are brought into practice, such as: (a) How will the languages for AMS assertions be different from the ones in the digital domain? (b) Does the analog simulator have to be assertion aware? (c) If so, then how and where on the time line will the AMS assertion checker synchronize with the analog simulator? and (d) What will be the performance penalty for monitoring AMS assertions accurately over analog simulation? This article attempts to answer these questions through theoretical analysis and empirical results obtained from industrial test cases. We study logics which extend Linear Temporal Logic (LTL) with predicates over real variables, and show that further extensions allowing the binding of real-valued variables across time makes the logic undecidable. We present a toolkit which can integrate with existing AMS simulators for checking AMS assertions on practical designs. We study the problem of synchronizing the AMS simulator with the AMS assertion checker and demonstrate the performance penalty of different synchronization options.