Reasoning about infinite computations
Information and Computation
An automata-theoretic approach to linear temporal logic
Proceedings of the VIII Banff Higher order workshop conference on Logics for concurrency : structure versus automata: structure versus automata
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Complexity of solvable cases of the decision problem for the predicate calculus
SFCS '78 Proceedings of the 19th Annual Symposium on Foundations of Computer Science
Finite automata and their decision problems
IBM Journal of Research and Development
Resets vs. aborts in linear temporal logic
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Synthesizing SVA local variables for formal verification
Proceedings of the 44th annual Design Automation Conference
Augmenting a regular expression-based temporal logic with local variables
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
On Regular Temporal Logics with Past,
ICALP '09 Proceedings of the 36th Internatilonal Collogquium on Automata, Languages and Programming: Part II
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
Untwist your brain: efficient debugging and diagnosis of complex assertions
Proceedings of the 46th Annual Design Automation Conference
Specification Languages for Stutter-Invariant Regular Properties
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SVA and PSL local variables - a practical approach
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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SystemVerilog Assertions (SVA) is a linear temporal logic within the recently approved IEEE 1800 SystemVerilog standard. The complexities of the satisfiability and model-checking problems are studied for a basic subset of (SVA) and for extensions of the basic subset obtained by adding each of the following features: local variables, regular expression intersection, quantified variables, and property declarations with arguments. It is shown that the complexities for the basic subset are PSPACE-complete, while the complexities increase to EXPSPACE-complete in each of the extensions. Alternating Büchi automata constructions provide the upper bounds, while reductions from PSPACE and EXPSPACE tiling problems provide the lower bounds.