A note on the reduction of two-way automata to one-way atuomata
Information Processing Letters
An automata-theoretic approach to linear temporal logic
Proceedings of the VIII Banff Higher order workshop conference on Logics for concurrency : structure versus automata: structure versus automata
Dynamic Logic
The complexity of propositional linear temporal logics in simple cases
Information and Computation
Another Look at LTL Model Checking
Formal Methods in System Design
Temporal Logic with Forgettable Past
LICS '02 Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Extended Temporal Logic Revisited
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Temporal Logic with Fixed Points
Temporal Logic in Specification
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Proceedings of the Conference on Logic of Programs
From PSL to NBA: a Modular Symbolic Encoding
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
A purely model-theoretic proof of the exponential succinctness gap between CTL+ and CTL
Information Processing Letters
Alternation Elimination by Complementation (Extended Abstract)
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Some complexity results for systemverilog assertions
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
PSL model checking and run-time verification via testers
FM'06 Proceedings of the 14th international conference on Formal Methods
Linear time logics around PSL: complexity, expressiveness, and a little bit of succinctness
CONCUR'07 Proceedings of the 18th international conference on Concurrency Theory
Specification Languages for Stutter-Invariant Regular Properties
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
A Trustworthy Usage Control Enforcement Framework
International Journal of Mobile Computing and Multimedia Communications
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The IEEE standardized Property Specification Language , PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL and the closely related SystemVerilog Assertions , SVA for short, are increasingly used in many phases of the hardware design cycle, from specification to verification. In this paper, we extend the common core of these specification languages with past operators. We name this extension RTL. Although all *** -regular properties are expressible in PSL, SVA, and RTL, past operators often allow one to specify properties more naturally and concisely. In fact, we show that RTL is exponentially more succinct than the cores of PSL and SVA. Furthermore, we present a translation of RTL into language-equivalent nondeterministic Büchi automata, which is based on novel constructions for 2-way alternating automata. Our translation has almost the same worst-case complexity in terms of the size of the resulting nondeterministic Büchi automata as the existing translations for PSL and SVA. Consequently, the satisfiability and the model-checking problem for RTL fall into the same complexity classes as the corresponding problems for PSL and SVA. From the translation it also follows that the blowup of translating RTL formulas into initially equivalent PSL/SVA formulas is at most triply exponential.