The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Embedding finite automata within regular expressions
Theoretical Computer Science
Augmenting a regular expression-based temporal logic with local variables
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Some complexity results for systemverilog assertions
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
| Hi-index | 0.00 |
SystemVerilog Assertions (SVA), as well as Property Specification Language (PSL) are linear temporal logics based on LTL [14], extended with regular expressions and local variables. In [6] Bustan and Havlicek show that the local variable extensions, as well as regular expressions with intersection, render the verification problem of SVA and PSL formulae EXPSPACE-complete. In this paper we show a practical approach for the verification problem of SVA and PSL with local variables. We show that in practice, for a significant and meaningful subsets of those languages, which we denote PSLpract, local variables do not increase the complexity of their verification problem, keeping it in PSPACE.