Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking

Authors:
Jens Schönherr;Martin Freibothe;Bernd Straube;Jörg Bormann
Affiliations:
Signalion GmbH, Sudhausweg 5, 01099 Dresden, Germany;Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division EAS, Zeunerstraβe 38, 01069 Dresden, Germany;Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division EAS, Zeunerstraβe 38, 01069 Dresden, Germany;OneSpin Solutions GmbH, Theresienhoehe 12, 80339 Munich, Germany
Venue:
Theoretical Computer Science
Year:
2008

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Abstract

In this article, a verification methodology for mixed-signal circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits.