Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Microprocessor design verification
Journal of Automated Reasoning
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Higher order logic and hardware verification
Higher order logic and hardware verification
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Description Methodology for Parameterized Modules in the Boyer-Moore Logic
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
Describing and verifying synchronous circuits with the Boyer-Moore theorem prover
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Formal verification of a PowerPC microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A symbolic core approach to the formal verification of integrated mixed-mode applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Theoretical Computer Science
Formal Verification of the Quasi-Static Behavior of Mixed-Signal Circuits by Property Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
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In this paper, a symbolic modelling approach is presented for the formal representation and verification of mixed analog/digital systems. The proposed modelling technique can be incorporated in the SFG-Tracing - a pragmatic methodology originally aimed at the formal verification of digital (VLSI) designs. Existing symbolic analysis and reasoning techniques can be employed to analyse the digital subsystems of a mixed analog/digital design. The development of appropriate, symbolic models to express the functional behaviour of the individual analog components, ultimately enables us to exploit a symbolic evaluation or simulation tool to formally verify the overall functional behaviour of a mixed-mode system.