Model checking
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms
Electronic Notes in Theoretical Computer Science (ENTCS)
PHAVer: algorithmic verification of hybrid systems past hytech
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
Instrumenting AMS assertion verification on commercial platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper we firstly introduce a novel symbolic model checker (MScheck) for mixed-signal circuits. MScheck is capable to conflate the continuous behavior, typical for analog designs, and the discrete behavior in the digital domain for formal verification. Timing information of both systems will be symbolically stored within multi terminal binary decision diagrams (MTBDDs) for the entire verification procedure. The effectiveness of our approach is demonstrated on a phase locked loop (PLL) by formal verification of the locking property1.