Analog system verification in the presence of parasitics using behavioral simulation
DAC '93 Proceedings of the 30th international Design Automation Conference
Behavioral simulation for analog system design verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A formal approach to nonlinear analog circuit verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Macromodeling of the A.C. characteristics of CMOS Op-amps
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Formal Verification of Synthesized Analog Designs
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Verification of transient response of linear analog circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Hi-index | 0.00 |
This paper develops a new formal technique to verify the frequency response of analog circuits using global optimization techniques. Since simulation-based approaches are unable to cover the design space, there is a need for formal approaches to verify large circuits. Drawing parallels from the digital domain, the verification problem in the analog domain is modeled as a non-linear optimization problem and solved using global optimization techniques by ensuring that the implementation response is bounded within an envelope around the specification. We also address the problem of verifying frequency response under the influence of parameter variations. Direct as well as indirect techniques are illustrated using accurate frequency response models. Experimental results are presented to show the effectiveness of the proposed methodology.