Collection and Analysis of Microprocessor Design Errors
IEEE Design & Test
Basic Concepts and Taxonomy of Dependable and Secure Computing
IEEE Transactions on Dependable and Secure Computing
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Deriving a unified fault taxonomy for event-based systems
Proceedings of the 6th ACM International Conference on Distributed Event-Based Systems
Safety demonstration and software development
SAFECOMP'07 Proceedings of the 26th international conference on Computer Safety, Reliability, and Security
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The rapid increase of the complexity of high-performance COTS (Commercial Off-The-Shelf) microprocessors has led to continuing post-design discoveries of numerous design faults, called "errata" by the manufacturers. This paper presents a systematic framework, the Design Fault Taxonomy, for the study of such design faults. Based on the proposed methodology, an in-depth analysis of design faults uncovered in the Intel Pentium y II microprocessor since its initial release is presented in detail. The results raise concerns about the use of such processors in high-confidence systems and point to potential solutions.