Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
| Hi-index | 0.00 |
Intel® Core™ microprocessors, including Xeon® 5100 (codenamed Woodcrest) and Core™ 2 Duo (code named Conroe and Merom), was the first Intel® Converged Core product which simultaneously hit all market segments (server, desktop and mobile platforms). A year after these microprocessors have successfully entered the market and significantly improved Intel® revenues and competitive position, it is time to analyze the post silicon validation experience. This paper discusses the Core processor's validation challenges, among them were: Very aggressive delivery schedule. The parallel validation of three market segment products within a one year time frame (first silicon to Product Revenue Qualification). Dramatic difference of Core™ Architecture and micro-architecture from those of Pentium® 4 family microprocessors which held the desktop and server market segments for the prior six years. The paper describes the post silicon functional validation methodologies, on both the System Validation (SV) and Compatibility Validation (CV) disciplines, at Intel Corporation as well as original equipment manufacturer (OEM) engagements during the validation cycle. The validation strategy was to quickly ramp up the internal validation capabilities and uncover all silicon issues within Intel Corporation. The overall goal was to preserve the tight OEM partner development cycles from samples to launch. The paper summarizes the major results vs. expectations and key learning for the future products.