Branch history table prediction of moving target branches due to subroutine returns
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Analysis of branch prediction via data compression
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Accurate indirect branch prediction
Proceedings of the 25th annual international symposium on Computer architecture
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
Compressing Extended Program Traces Using Value Predictors
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
The VPC Trace-Compression Algorithms
IEEE Transactions on Computers
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
An efficient single-pass trace compression technique utilizing instruction streams
ACM Transactions on Modeling and Computer Simulation (TOMACS)
A real-time program trace compressor utilizing double move-to-front method
Proceedings of the 46th Annual Design Automation Conference
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Hardware-Based Load Value Trace Filtering for On-the-Fly Debugging
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
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Unobtrusive capturing of program execution traces in real-time is crucial in debugging cyber-physical systems. However, tracing even limited program segments is often cost-prohibitive, requiring wide trace ports and large on-chip trace buffers. This paper introduces a new cost-effective technique for capturing and compressing program execution traces in real time. It uses branch predictor-like structures in the trace module to losslessly compress the traces. This approach results in high compression ratios because it only has to transmit misprediction events to the software debugger. Coupled with an effective variable encoding scheme, our technique requires merely 0.036 bits/instruction of trace port bandwidth (a 28-fold improvement over the commercial state-of-the-art) at a cost of roughly 5,200 logic gates.