Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Journal of the ACM (JACM)
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The Odd-Even Turn Model for Adaptive Routing
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Introduction to Reinforcement Learning
Introduction to Reinforcement Learning
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A low latency router supporting adaptivity for on-chip interconnects
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Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
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Globally Adaptive Load-Balanced Routing on Tori
IEEE Computer Architecture Letters
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
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Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
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Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Network Congestion-Aware Memory Controller
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the Third International Workshop on Network on Chip Architectures
NoCs Simulation Framework for OMNeT++
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Proceedings of the 38th annual international symposium on Computer architecture
Q-learning based congestion-aware routing algorithm for on-chip network
NESEA '11 Proceedings of the 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks
NOCS '12 Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
Optimized Q-learning model for distributing traffic in on-Chip Networks
NESEA '12 Proceedings of the 2012 IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)
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Network congestion has a negative impact on the performance of on-chip networks due to the increased packet latency. Many congestion-aware routing algorithms have been developed to alleviate traffic congestion over the network. In this paper, we propose a congestion-aware routing algorithm based on the Q-learning approach for avoiding congested areas in the network. By using the learning method, local and global congestion information of the network is provided for each switch. This information can be dynamically updated, when a switch receives a packet. However, Q-learning approach suffers from high area overhead in NoCs due to the need for a large routing table in each switch. In order to reduce the area overhead, we also present a clustering approach that decreases the number of routing tables by the factor of 4. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms.