CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Smart hill climbing for agile dynamic mapping in many-core systems
Proceedings of the 50th Annual Design Automation Conference
Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs
Microprocessors & Microsystems
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the occurrence of congestion in on-chip networks can severely degrade the performance due to increased message latency. In mesh topology, minimal methods can propagate messages over two directions at each switch. When shortest paths are congested, sending more messages through them can deteriorate the congestion condition considerably. In this paper, we present an adaptive routing algorithm for on-chip networks that provide a wide range of alternative paths between each pair of source and destination switches. Initially, the algorithm determines all permitted turns in the network including 180-degree turns on a single channel without creating cycles. The implementation of the algorithm provides the best usage of all allowable turns to route messages more adaptively in the network. On top of that, for selecting a less congested path, an optimized and scalable learning method is utilized. The learning method is based on local and global congestion information and can estimate the latency from each output channel to the destination region.