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This paper presents a method for designing SystemC-compliantInstruction Set Simulators (ISS) that address three of the majorproblems system designers are faced with when modeling MP-SoCsarchitectures: the multiple levels of abstraction of the simulationmodels supporting the design space exploration, the simulation speed,and the debug of the multithreaded embedded application. First, thispaper presents the ISS API and principles; then it describes howthe same ISS can support SystemC simulation at several abstractionlevels: untimed transaction level, approximately timed transactionlevel, and cycle accurate; then, it describes how the proposed ISS APIhas been used by six different laboratories - in the framework of theSoCLib project - to share the same L1 cache simulation model, and towrap seven different processor cores in the same generic wrappers.Finally we demonstrate how the proposed API has been exploited todevelop a generic debug and instrumentationinfrastructure that can be used for all the processor cores, and allthe abstraction levels supported by the SoCLib virtual prototypingplatform.